185
CY7C185
8K x 8 Static RAM
provided by an active LOW chip enable (CE ), an active HIGH
Features
1
chip enable (CE ), and active LOW output enable (OE) and
2
• High speed
— 15 ns
three-state drivers. This device has an automatic power-down
feature (CE or CE ), reducing the power consumption by 70%
1
2
when deselected. The CY7C185 is in a standard 300-mil-wide
DIP, SOJ, or SOIC package.
• Fast t
DOE
• Low active power
An active LOW write enable signal (WE) controls the writ-
— 715 mW
ing/reading operation of the memory. When CE and WE in-
1
• Low standby power
puts are both LOW and CE is HIGH, data on the eight data
2
input/output pins (I/O through I/O ) is written into the memory
0
7
— 220 mW
location addressed by the address present on the address
• CMOS for optimum speed/power
• Easy memory expansion with CE , CE , and OE features
pins (A through A ). Reading the device is accomplished by
0
12
selecting the device and enabling the outputs, CE and OE
1
2
1
• TTL-compatible inputs and outputs
• Automatic power-down when deselected
active LOW, CE active HIGH, while WE remains inactive or
2
HIGH. Under these conditions, the contents of the location ad-
dressed by the information on address pins are present on the
eight data input/output pins.
Functional Description[1]
The input/output pins remain in a high-impedance state unless
the chip is selected, outputs are enabled, and write enable
(WE) is HIGH. A die coat is used to insure alpha immunity.
The CY7C185 is a high-performance CMOS static RAM orga-
nized as 8192 words by 8 bits. Easy memory expansion is
Logic Block Diagram
Pin Configurations
DIP/SOJ/SOIC
Top View
NC
V
CC
1
2
3
4
28
27
26
25
24
23
22
21
20
19
18
17
16
15
A
WE
CE
4
A
5
2
A
A
3
6
A
A
2
A
1
7
5
I/O
I/O
0
A
8
6
7
8
9
10
11
12
13
14
A
9
OE
INPUT BUFFER
A
A
A
A
0
10
11
12
1
CE
1
I/O
7
I/O
6
I/O
5
I/O
4
I/O
3
A
1
A
2
I/O
0
I/O
1
I/O
2
I/O
I/O
2
A
3
3
GND
A
256 x 32 x 8
ARRAY
4
A
5
I/O
I/O
I/O
I/O
4
5
6
7
A
6
A
7
A
8
POWER
DOWN
CE
1
COLUMN DECODER
CE
2
WE
OE
Selection Guide[2]
7C185-15
15
7C185-20
20
7C185-25
25
7C185-35
35
Maximum Access Time (ns)
Maximum Operating Current (mA)
130
110
100
100
Maximum Standby Current (mA)
40/15
20/15
20/15
20/15
Note:
1. For guidelines on SRAM system design, please refer to the ‘System Design Guidelines’ Cypress application note, available on the internet at www.cypress.com.
2. For military specifications, see the CY7C185A data sheet.
Cypress Semiconductor Corporation
•
3901 North First Street
•
San Jose
•
CA 95134
•
408-943-2600
Document #: 38-05043 Rev. *A
Revised September 13, 2002
CY7C185
Electrical Characteristics Over the Operating Range (continued)
7C185-25
7C185-35
Parameter
Description
Test Conditions
= Min., I = –4.0 mA
Min.
Max.
Min.
Max.
Unit
V
V
Output HIGH Voltage
Output LOW Voltage
Input HIGH Voltage
V
V
2.4
2.4
OH
OL
IH
CC
OH
V
V
= Min., I = 8.0 mA
0.4
0.4
V
CC
OL
2.2
V
+
2.2
V
+
V
CC
CC
0.3V
0.3V
[3]
V
Input LOW Voltage
–0.5
–5
0.8
+5
+5
–0.5
–5
0.8
+5
+5
V
IL
I
I
Input Load Current
GND ≤ V ≤ V
CC
µA
µA
IX
I
Output Leakage
Current
GND ≤ V ≤ V ,
CC
–5
–5
OZ
I
Output Disabled
I
I
I
I
Output Short
Circuit Current
V
V
= Max.,
–300
100
20
–300
100
20
mA
mA
mA
mA
OS
CC
[4]
= GND
OUT
V
Operating
V
= Max.,
= 0 mA
CC
CC
CC
Supply Current
I
OUT
Automatic
Power-Down Current
Max. V , CE ≥ V or CE ≤ V
CC IH IL
Min. Duty Cycle = 100%
SB1
SB2
1
2
Automatic
Max. V , CE ≥ V – 0.3V
15
15
CC
1
CC
Power-Down Current
or CE ≤ 0.3V
2
V
≥ V – 0.3V or V ≤ 0.3V
IN
CC IN
Capacitance[5]
Parameter
Description
Input Capacitance
Output Capacitance
Test Conditions
T = 25°C, f = 1 MHz,
Max.
Unit
C
C
7
7
pF
pF
IN
A
V
= 5.0V
CC
OUT
Note:
5. Tested initially and after any design or process changes that may affect these parameters.
AC Test Loads and Waveforms
R1 481Ω
R1 481Ω
5V
5V
ALL INPUT PULSES
90%
OUTPUT
OUTPUT
3.0V
GND
90%
10%
30 pF
5 pF
R2
255Ω
R2
255Ω
10%
INCLUDING
JIG AND
SCOPE
INCLUDING
JIGAND
≤ 5 ns
≤ 5 ns
SCOPE
(a)
(b)
Equivalent to:
THÉVENIN EQUIVALENT
167Ω
OUTPUT
1.73V
Document #: 38-05043 Rev. *A
Page 3 of 11
CY7C185
[6]
Switching Characteristics Over the Operating Range
7C185-15
Min. Max.
7C185-20
Min. Max.
7C185-25
Min. Max.
7C185-35
Min. Max.
Parameter
Description
Unit
Read Cycle
t
t
t
t
t
t
t
t
t
t
t
Read Cycle Time
15
3
20
5
25
5
35
5
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
RC
Address to Data Valid
15
20
25
35
AA
Data Hold from Address Change
OHA
CE LOW to Data Valid
15
15
8
20
20
9
25
25
12
35
35
15
ACE1
ACE2
DOE
1
CE HIGH to Data Valid
2
OE LOW to Data Valid
OE LOW to Low Z
3
3
3
3
LZOE
HZOE
LZCE1
LZCE2
HZCE
[7]
OE HIGH to High Z
7
7
8
8
10
10
10
10
[8]
CE LOW to Low Z
3
3
5
3
5
3
5
3
1
CE HIGH to Low Z
2
[7, 8]
CE HIGH to High Z
1
CE LOW to High Z
2
t
t
CE LOW to Power-Up
0
0
0
0
ns
ns
PU
PD
1
CE to HIGH to Power-Up
2
CE HIGH to Power-Down
15
20
20
20
1
CE LOW to Power-Down
2
[9]
Write Cycle
t
t
t
t
t
t
t
t
t
t
t
Write Cycle Time
15
12
12
12
0
20
15
15
15
0
25
20
20
20
0
35
20
20
25
0
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
WC
CE LOW to Write End
SCE1
SCE2
AW
1
CE HIGH to Write End
2
Address Set-up to Write End
Address Hold from Write End
Address Set-up to Write Start
WE Pulse Width
HA
0
0
0
0
SA
12
8
15
10
0
15
10
0
20
12
0
PWE
SD
Data Set-up to Write End
Data Hold from Write End
0
HD
[7]
WE LOW to High Z
7
7
7
8
HZWE
WE HIGH to Low Z
3
5
5
5
LZWE
Notes:
6. Test conditions assume signal transition time of 5 ns or less, timing reference levels of 1.5V, input pulse levels of 0 to 3.0V, and output loading of the specified
IOL/IOH and 30-pF load capacitance.
7. tHZOE, tHZCE, and tHZWE are specified with CL = 5 pF as in part (b) of AC Test Loads. Transition is measured ±500 mV from steady state voltage.
8. At any given temperature and voltage condition, tHZCE is less than tLZCE1 and tLZCE2 for any given device.
9. The internal write time of the memory is defined by the overlap of CE1 LOW, CE2 HIGH, and WE LOW. All 3 signals must be active to initiate a write and either
signal can terminate a write by going HIGH. The data input set-up and hold timing should be referenced to the rising edge of the signal that terminates the write.
Document #: 38-05043 Rev. *A
Page 4 of 11
CY7C185
Switching Waveforms
[10,11]
Read Cycle No.1
t
RC
ADDRESS
t
AA
t
OHA
DATA OUT
PREVIOUS DATA VALID
DATA VALID
[12,13]
Read Cycle No.2
t
RC
CE
1
CE
2
t
ACE
OE
t
HZOE
t
DOE
t
HZCE
t
LZOE
HIGH
IMPEDANCE
HIGH IMPEDANCE
DATA OUT
DATA VALID
t
LZCE
t
PD
t
PU
ICC
ISB
V
CC
SUPPLY
CURRENT
50%
50%
[11,13]
Write Cycle No. 1 (WE Controlled)
t
WC
ADDRESS
t
CE
1
SCEI
t
t
HA
AW
t
CE
SCE2
2
t
SA
t
PWE
WE
OE
t
SD
t
HD
DATA VALID
NOTE 14
t
IN
DATA I/O
HZOE
10. Device is continuously selected. OE, CE1 = VIL. CE2 = VIH
.
11. WE is HIGH for read cycle.
12. Data I/O is High Z if OE = VIH, CE1 = VIH, WE = VIL, or CE2=VIL
.
13. The internal write time of the memory is defined by the overlap of CE1 LOW, CE2 HIGH and WE LOW. CE1 and WE must be LOW and CE2 must be HIGH
to initiate write. A write can be terminated by CE1 or WE going HIGH or CE2 going LOW. The data input set-up and hold timing should be referenced to the
rising edge of the signal that terminates the write.
14. During this period, the I/Os are in the output state and input signals should not be applied.
Document #: 38-05043 Rev. *A
Page 5 of 11
CY7C185
Switching Waveforms (continued)
[13,14,15]
rite Cycle No. 2 (CE Controlled)
t
WC
ADDRESS
t
t
CE
1
SCE1
t
SA
SCE2
CE
2
t
t
HA
AW
WE
t
t
HD
SD
DATA VALID
DATA I/O
IN
[13,14,15,16]
Write Cycle No. 3 (WE Controlled, OE LOW)
t
WC
ADDRESS
t
CE
SCE1
1
t
CE
SCE2
2
t
t
HA
AW
t
SA
WE
t
t
HD
SD
DATA I/O
DATA VALID
NOTE 14
IN
t
t
LZWE
HZWE
Notes:
15. The minimum write cycle time for write cycle #3 (WE controlled, OE LOW) is the sum of tHZWE and tSD
.
16. If CE1 goes HIGH or CE2 goes LOW simultaneously with WE HIGH, the output remains in a high-impedance state.
Document #: 38-05043 Rev. *A
Page 6 of 11
CY7C185
Typical DC and AC Characteristics
NORMALIZED SUPPLY CURRENT
vs. AMBIENT TEMPERATURE
OUTPUT SOURCE CURRENT
vs. OUTPUT VOLTAGE
NORMALIZED SUPPLY CURRENT
vs. SUPPLY VOLTAGE
120
100
80
1.4
1.2
1.0
1.2
1.0
0.8
I
I
CC
CC
0.8
0.6
0.4
V
T
A
=5.0V
=25°C
CC
0.6
0.4
60
40
V
V
=5.0V
=5.0V
CC
IN
0.2
0.0
20
0
I
0.2
0.0
SB
I
SB
–55
25
125
0.0
1.0
2.0
3.0
4.0
4.0
4.5
5.0
5.5
6.0
AMBIENT TEMPERATURE (°C)
OUTPUT VOLTAGE (V)
SUPPLY VOLTAGE (V)
NORMALIZED ACCESS TIME
vs. AMBIENT TEMPERATURE
OUTPUT SINK CURRENT
vs. OUTPUT VOLTAGE
NORMALIZED ACCESS TIME
vs. SUPPLY VOLTAGE
140
120
1.6
1.4
1.4
1.3
1.2
100
80
V
CC
=5.0V
1.2
1.0
T =25°C
A
1.1
1.0
60
T =25°C
A
V
CC
=5.0V
40
0.8
20
0
0.9
0.8
0.6
–55
0.0
1.0
2.0
3.0
4.0
25
125
4.0
4.5
5.0
5.5
6.0
OUTPUT VOLTAGE (V)
SUPPLY VOLTAGE (V)
AMBIENT TEMPERATURE (°C)
TYPICAL POWER-ON CURRENT
vs. SUPPLY VOLTAGE
TYPICAL ACCESS TIME CHANGE
vs. OUTPUT LOADING
NORMALIZED I vs. CYCLE TIME
CC
3.0
2.5
2.0
1.5
30.0
25.0
20.0
15.0
1.25
1.00
0.75
0.50
V
=5.0V
CC
T =25°C
A
V
CC
=0.5V
1.0
0.5
0.0
10.0
5.0
V
=4.5V
CC
T =25°C
A
0.0
0.0
1.0
2.0
3.0
4.0
5.0
0
200 400
600 800 1000
10
20
30
40
SUPPLY VOLTAGE (V)
CAPACITANCE (pF)
CYCLE FREQUENCY (MHz)
Document #: 38-05043 Rev. *A
Page 7 of 11
CY7C185
Truth Table
CE
H
X
CE
X
WE
X
OE
X
Input/Output
Mode
Deselect/Power-Down
1
2
High Z
High Z
L
X
X
Deselect/Power-Down
L
H
H
L
Data Out
Data In
High Z
Read
L
H
L
X
Write
L
H
H
H
Deselect
Address Designators
Address
Name
Address
Function
Pin
Number
A4
A5
X3
X4
X5
X6
X7
Y1
Y4
Y3
Y0
Y2
X0
X1
X2
2
3
A6
4
A7
5
A8
6
A9
7
A10
A11
A12
A0
8
9
10
21
23
24
25
A1
A2
A3
Ordering Information
Speed
(ns)
Package
Name
Operating
Range
Ordering Code
Package Type
15
CY7C185-15PC
CY7C185-15SC
CY7C185-15VC
CY7C185-15VI
CY7C185-20PC
CY7C185-20SC
CY7C185-20VC
CY7C185-20VI
CY7C185-25PC
CY7C185-25SC
CY7C185-25VC
CY7C185-25VI
CY7C185-35PC
CY7C185-35SC
CY7C185-35VC
CY7C185-35VI
P21
S21
V21
V21
P21
S21
V21
V21
P21
S21
V21
V21
P21
S21
V21
V21
28-Lead (300-Mil) Molded DIP
28-Lead Molded SOIC
28-Lead Molded SOJ
Commercial
28-Lead Molded SOJ
Industrial
20
25
35
28-Lead (300-Mil) Molded DIP
28-Lead Molded SOIC
28-Lead Molded SOJ
Commercial
28-Lead Molded SOJ
Industrial
28-Lead (300-Mil) Molded DIP
28-Lead Molded SOIC
28-Lead Molded SOJ
Commercial
28-Lead Molded SOJ
Industrial
28-Lead (300-Mil) Molded DIP
28-Lead Molded SOIC
28-Lead Molded SOJ
Commercial
28-Lead Molded SOJ
Industrial
Document #: 38-05043 Rev. *A
Page 8 of 11
CY7C185
Package Diagrams
28-Lead (300-Mil) Molded DIP P21
51-85014-*B
28-Lead (300-Mil) Molded SOIC S21
51-85026-*A
Document #: 38-05043 Rev. *A
Page 9 of 11
CY7C185
Package Diagrams (continued)
28-Lead (300-Mil) Molded SOJ V21
51-85031-*B
All product and company names mentioned in this document may be the trademarks of their respective holders.
Document #: 38-05043 Rev. *A
Page 10 of 11
© Cypress Semiconductor Corporation, 2002. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use
of any circuitry other than circuitry embodied in a Cypress Semiconductor product. Nor does it convey or imply any license under patent or other rights. Cypress Semiconductor does not authorize
its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress
Semiconductor products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress Semiconductor against all charges.
CY7C185
Document History Page
Document Title: CY7C185 8K x 8 Static RAM
Document Number: 38-05043
Issue
Orig. of
Change
REV.
**
*A
ECN NO. Date
Description of Change
107145
116470
09/10/01
09/16/02
SZV
CEA
Change from Spec number: 38-00037 to 38-05043
Add applications foot note to data sheet.
Document #: 38-05043 Rev. *A
Page 11 of 11
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