Cypress Computer Hardware STK22C48 User Manual

STK22C48  
16 Kbit (2K x 8) AutoStore nvSRAM  
Features  
Functional Description  
25 ns and 45 ns access times  
The Cypress STK22C48 is a fast static RAM with a nonvolatile  
element in each memory cell. The embedded nonvolatile  
Hands off automatic STORE on power down with external 68  
µF capacitor  
elements incorporate QuantumTrap technology producing the  
world’s most reliable nonvolatile memory. The SRAM provides  
unlimited read and write cycles, while independent nonvolatile  
data resides in the highly reliable QuantumTrap cell. Data  
transfers from the SRAM to the nonvolatile elements (the  
STORE operation) takes place automatically at power down. On  
power up, data is restored to the SRAM (the RECALL operation)  
from the nonvolatile memory. A hardware STORE is initiated with  
the HSB pin.  
STORE to QuantumTrap™ nonvolatile elements is initiated by  
software, hardware, or AutoStore™ on power down  
RECALL to SRAM initiated by software or power up  
Unlimited Read, Write, and Recall cycles  
1,000,000 STORE cycles to QuantumTrap  
100 year data retention to QuantumTrap  
Single 5V+10% operation  
Commercial and industrial temperatures  
28-pin 300 mil and (330 mil) SOIC package  
RoHS compliance  
Logic Block Diagram  
V
V
CC  
CAP  
Quantum Trap  
32 X 512  
POWER  
A5  
STORE  
CONTROL  
A6  
RECALL  
STORE/  
RECALL  
CONTROL  
STATIC RAM  
ARRAY  
32 X 512  
A7  
A8  
HSB  
A9  
DQ0  
COLUMN I/O  
DQ1  
DQ2  
DQ3  
COLUMN DEC  
DQ4  
DQ5  
DQ6  
DQ7  
A0  
A4  
A10  
A1  
A3  
A2  
OE  
CE  
WE  
Cypress Semiconductor Corporation  
Document Number: 001-51000 Rev. **  
198 Champion Court  
San Jose, CA 95134-1709  
408-943-2600  
Revised January 30, 2009  
 
STK22C48  
Figure 2. AutoStore Mode  
Device Operation  
The STK22C48 nvSRAM is made up of two functional compo-  
nents paired in the same physical cell. These are an SRAM  
memory cell and a nonvolatile QuantumTrap cell. The SRAM  
memory cell operates as a standard fast static RAM. Data in the  
SRAM is transferred to the nonvolatile cell (the STORE  
operation) or from the nonvolatile cell to SRAM (the RECALL  
operation). This unique architecture enables the storage and  
recall of all cells in parallel. During the STORE and RECALL  
operations, SRAM Read and Write operations are inhibited. The  
STK22C48 supports unlimited reads and writes similar to a  
typical SRAM. In addition, it provides unlimited RECALL opera-  
tions from the nonvolatile cells and up to one million STORE  
operations.  
9&$3  
9FF  
:(  
+6%  
SRAM Read  
The STK22C48 performs a Read cycle whenever CE and OE are  
LOW while WE and HSB are HIGH. The address specified on  
pins A  
determines the 2,048 data bytes accessed. When the  
0–10  
Read is initiated by an address transition, the outputs are valid  
after a delay of t (Read cycle 1). If the Read is initiated by CE  
AA  
or OE, the outputs are valid at t  
or at t  
, whichever is later  
ACE  
DOE  
9VV  
(Read cycle 2). The data outputs repeatedly respond to address  
changes within the t access time without the need for transi-  
AA  
tions on any control input pins, and remains valid until another  
address change or until CE or OE is brought HIGH, or WE or  
HSB is brought LOW.  
In system power mode, both V and V  
are connected to the  
CAP  
CC  
+5V power supply without the 68 μF capacitor. In this mode, the  
AutoStore function of the STK22C48 operates on the stored  
system charge as power goes down. The user must, however,  
SRAM Write  
guarantee that V does not drop below 3.6V during the 10 ms  
CC  
STORE cycle.  
A Write cycle is performed whenever CE and WE are LOW and  
HSB is HIGH. The address inputs must be stable prior to entering  
the Write cycle and must remain stable until either CE or WE  
goes HIGH at the end of the cycle. The data on the common IO  
To prevent unneeded STORE operations, automatic STOREs  
and those initiated by externally driving HSB LOW are ignored,  
unless at least one WRITE operation takes place since the most  
recent STORE or RECALL cycle. An optional pull up resistor is  
shown connected to HSB. This is used to signal the system that  
the AutoStore cycle is in progress.  
pins DQ  
are written into the memory if it has valid t , before  
0–7  
SD  
the end of a WE controlled Write or before the end of an CE  
controlled Write. Keep OE HIGH during the entire Write cycle to  
avoid data bus contention on common IO lines. If OE is left LOW,  
internal circuitry turns off the output buffers t  
LOW.  
after WE goes  
AutoStore Inhibit mode  
HZWE  
If an automatic STORE on power loss is not required, then V  
CC  
AutoStore Operation  
is tied to ground and +5V is applied to V  
(Figure 3). This is  
CAP  
the AutoStore Inhibit mode, where the AutoStore function is  
disabled. If the STK22C48 is operated in this configuration, refer-  
During normal operation, the device draws current from V to  
charge a capacitor connected to the V  
CC  
pin. This stored  
ences to V are changed to V  
throughout this data sheet.  
CAP  
CC  
CAP  
charge is used by the chip to perform a single STORE operation.  
If the voltage on the V pin drops below V , the part  
In this mode, STORE operations are triggered with the HSB pin.  
It is not permissible to change between these three options “on  
the fly”.  
CC  
SWITCH  
automatically disconnects the V  
operation is initiated with power provided by the V  
pin from V . A STORE  
CAP  
CC  
capacitor.  
CAP  
Figure 2 shows the proper connection of the storage capacitor  
(V ) for automatic store operation. A charge storage capacitor  
CAP  
between 68 µF and 220 µF (+20%) rated at 6V should be  
Document Number: 001-51000 Rev. **  
Page 3 of 14  
 
 
STK22C48  
Figure 3. AutoStore Inhibit Mode  
Data Protection  
The STK22C48 protects data from corruption during low voltage  
conditions by inhibiting all externally initiated STORE and Write  
operations. The low voltage condition is detected when V is  
CC  
less than V  
. If the STK22C48 is in a Write mode (both CE  
9&$3  
9FF  
:(  
SWITCH  
and WE are low) at power up after a RECALL or after a STORE,  
the Write is inhibited until a negative transition on CE or WE is  
detected. This protects against inadvertent writes during power  
up or brown out conditions.  
+6%  
Noise Considerations  
The STK22C48 is a high speed memory. It must have a high  
frequency bypass capacitor of approximately 0.1 µF connected  
between V and V  
using leads and traces that are as short  
CC  
SS,  
as possible. As with all high speed CMOS ICs, careful routing of  
power, ground, and signals reduce circuit noise.  
Hardware Protect  
9VV  
The STK22C48 offers hardware protection against inadvertent  
STORE operation and SRAM Writes during low voltage condi-  
tions. When V  
<V  
, all externally initiated STORE  
CAP  
SWITCH  
operations and SRAM Writes are inhibited. AutoStore can be  
completely disabled by tying VCC to ground and applying +5V to  
Hardware STORE (HSB) Operation  
V
. This is the AutoStore Inhibit mode; in this mode, STOREs  
CAP  
The STK22C48 provides the HSB pin for controlling and  
acknowledging the STORE operations. The HSB pin is used to  
request a hardware STORE cycle. When the HSB pin is driven  
LOW, the STK22C48 conditionally initiates a STORE operation  
are only initiated by explicit request using either the software  
sequence or the HSB pin.  
Low Average Active Power  
after t  
. An actual STORE cycle only begins if a Write to the  
DELAY  
SRAM takes place since the last STORE or RECALL cycle. The  
HSB pin also acts as an open drain driver that is internally driven  
LOW to indicate a busy condition, while the STORE (initiated by  
any means) is in progress. Pull up this pin with an external 10K  
CMOS technology provides the STK22C48 the benefit of  
drawing significantly less current when it is cycled at times longer  
than 50 ns. Figure 4 shows the relationship between I  
and  
CC  
Read or Write cycle time. Worst case current consumption is  
shown for both CMOS and TTL input levels (commercial temper-  
ature range, VCC = 5.5V, 100% duty cycle on chip enable). Only  
standby current is drawn when the chip is disabled. The overall  
average current drawn by the STK22C48 depends on the  
following items:  
ohm resistor to V  
if HSB is used as a driver.  
CAP  
SRAM Read and Write operations, that are in progress when  
HSB is driven LOW by any means, are given time to complete  
before the STORE operation is initiated. After HSB goes LOW,  
the STK22C48 continues SRAM operations for t  
. During  
DELAY  
t
, multiple SRAM Read operations take place. If a Write is  
DELAY  
The duty cycle of chip enable  
The overall cycle rate for accesses  
The ratio of Reads to Writes  
CMOS versus TTL input levels  
The operating temperature  
in progress when HSB is pulled LOW, it allows a time, t  
complete. However, any SRAM Write cycles requested after  
HSB goes LOW are inhibited until HSB returns HIGH.  
to  
DELAY  
During any STORE operation, regardless of how it is initiated,  
the STK22C48 continues to drive the HSB pin LOW, releasing it  
only when the STORE is complete. After completing the STORE  
operation, the STK22C48 remains disabled until the HSB pin  
returns HIGH.  
The V level  
CC  
If HSB is not used, it is left unconnected.  
IO loading  
Hardware RECALL (Power Up)  
During power up or after any low power condition (V  
<
CC  
V
), an internal RECALL request is latched. When V  
RESET  
CC  
once again exceeds the sense voltage of V  
, a RECALL  
SWITCH  
cycle is automatically initiated and takes t  
to complete.  
HRECALL  
Document Number: 001-51000 Rev. **  
Page 4 of 14  
 
 
STK22C48  
Figure 4. Current Versus Cycle Time (Read)  
device drives HSB LOW for 20 ns at the onset of a STORE.  
When the STK22C48 is connected for AutoStore operation  
(system V connected to V and a 68 μF capacitor on V )  
CC  
crosses V  
CC  
CAP  
and V  
on the way down, the STK22C48  
CC  
SWITCH  
attempts to pull HSB LOW. If HSB does not actually get below  
V , the part stops trying to pull HSB LOW and abort the STORE  
IL  
attempt.  
Best Practices  
nvSRAM products have been used effectively for over 15 years.  
While ease of use is one of the product’s main system values,  
experience gained working with hundreds of applications has  
resulted in the following suggestions as best practices:  
The nonvolatile cells in an nvSRAM are programmed on the  
test floor during final test and quality assurance. Incoming  
inspection routines at customer or contract manufacturer’s  
sitessometimesreprogramthesevalues. FinalNVpatternsare  
typically repeating patterns of AA, 55, 00, FF, A5, or 5A. The  
end product’s firmware should not assume that an NV array is  
in a set programmed state. Routines that check memory  
content values to determine first time system configuration,  
cold or warm boot status, and so on must always program a  
unique NV pattern (for example, complex 4-byte pattern of 46  
E6 49 53 hex or more random bytes) as part of the final system  
manufacturing test to ensure these system routines work  
consistently.  
Figure 5. Current Versus Cycle Time (Write)  
Power up boot firmware routines should rewrite the nvSRAM  
into the desired state. While the nvSRAM is shipped in a preset  
state, best practice is to again rewrite the nvSRAM into the  
desired state as a safeguard against events that might flip the  
bit inadvertently (program bugs, incoming inspection routines,  
and so on).  
TheV  
valuespecifiedinthisdatasheetincludesaminimum  
CAP  
and a maximum value size. The best practice is to meet this  
requirementandnotexceedthemaximumV valuebecause  
CAP  
the higher inrush currents may reduce the reliability of the  
internal pass transistor. Customers who want to use a larger  
Preventing Store  
V
value to make sure there is extra store charge should  
The STORE function is disabled by holding HSB high with a  
CAP  
discuss their V  
size selection with Cypress.  
driver capable of sourcing 30 mA at a V  
of at least 2.2V,  
CAP  
OH  
because it must overpower the internal pull down device. This  
Table 2. Hardware Mode Selection  
CE  
H
L
WE  
X
HSB  
H
A10–A0  
Mode  
IO  
Power  
X
X
X
X
Not Selected  
Read SRAM  
Output High Z  
Output Data  
Input Data  
Standby  
[1]  
H
H
Active  
L
L
H
Write SRAM  
Active  
X
X
L
Nonvolatile STORE  
Output High Z  
I
CC2  
Notes  
1. I/O state assumes OE < V . Activation of nonvolatile cycles does not depend on state of OE.  
IL  
2. HSB STORE operation occurs only if an SRAM Write is done since the last nonvolatile cycle. After the STORE (If any) completes, the part goes into standby mode,  
inhibiting all operations until HSB rises.  
Document Number: 001-51000 Rev. **  
Page 5 of 14  
 
     
STK22C48  
Voltage on DQ or HSB .......................–0.5V to Vcc + 0.5V  
Maximum Ratings  
0-7  
Power Dissipation ......................................................... 1.0W  
DC Output Current (1 output at a time, 1s duration).... 15 mA  
Exceeding maximum ratings may shorten the useful life of the  
device. These user guidelines are not tested.  
Storage Temperature ................................. –65°C to +150°C  
Temperature under bias.............................. –55°C to +125°C  
Operating Range  
Range  
Commercial  
Industrial  
Ambient Temperature  
0°C to +70°C  
V
CC  
Supply Voltage on V Relative to GND ..........–0.5V to 7.0V  
CC  
4.5V to 5.5V  
4.5V to 5.5V  
Voltage on Input Relative to Vss............0.6V to V + 0.5V  
CC  
-40°C to +85°C  
DC Electrical Characteristics  
Over the operating range (V = 4.5V to 5.5V)  
CC  
Parameter  
Description  
Average V Current  
Test Conditions  
Min  
Max  
Unit  
I
t
t
= 25 ns  
= 45 ns  
Commercial  
Industrial  
85  
65  
mA  
mA  
CC1  
CC  
RC  
RC  
Dependent on output loading and cycle  
rate. Values obtained without output loads.  
90  
65  
mA  
mA  
I
= 0 mA.  
OUT  
I
I
Average V Current during  
STORE  
All Inputs Do Not Care, V = Max  
3
mA  
mA  
CC2  
CC  
CC  
Average current for duration t  
STORE  
Average V Current at t  
=
WE > (V – 0.2V). All other inputs cycling.  
10  
CC3  
CC  
RC  
CC  
200 ns, 5V, 25°C Typical  
Dependent on output loading and cycle rate. Values  
obtained without output loads.  
I
I
Average V  
AutoStore Cycle  
Current during  
All Inputs Do Not Care, V = Max  
2
mA  
CC4  
CAP  
CC  
Average current for duration t  
STORE  
Average Vcc Current  
(Standby, Cycling TTL Input  
Levels)  
t
t
= 25 ns, CE > V  
= 45 ns, CE > V  
Commercial  
Industrial  
25  
18  
mA  
mA  
SB1  
RC  
RC  
IH  
IH  
26  
19  
mA  
mA  
I
V
Standby Current  
CE > (V – 0.2V). All others V < 0.2V or > (V – 0.2V).  
1.5  
mA  
SB2  
CC  
CC  
IN  
CC  
Standby current level after nonvolatile cycle is complete.  
Inputs are static. f = 0 MHz.  
I
I
Input Leakage Current  
V
V
= Max, V < V < V  
CC  
-1  
-5  
+1  
+5  
μA  
μA  
ILK  
CC  
CC  
SS  
IN  
Off State Output Leakage  
Current  
= Max, V < V < V , CE or OE > V or WE < V  
SS IN CC IH IL  
OLK  
V
Input HIGH Voltage  
2.2  
V
0.5  
+
V
IH  
CC  
V
V
V
V
V
Input LOW Voltage  
Output HIGH Voltage  
Output LOW Voltage  
V
– 0.5  
0.8  
V
V
IL  
SS  
I
I
= –4 mA except HSB  
= 8 mA except HSB  
= 3 mA  
2.4  
61  
OH  
OL  
BL  
OUT  
OUT  
OUT  
0.4  
0.4  
V
Logic ‘0’ Voltage on HSB Output I  
Storage Capacitor  
V
Between V  
nom.  
pin and Vss, 6V rated. 68 uF -10%, +20%  
CAP  
220  
µF  
CAP  
Data Retention and Endurance  
Parameter  
Description  
Min  
Unit  
DATA  
Data Retention  
100  
Years  
K
R
NV  
Nonvolatile STORE Operations  
1,000  
C
Notes  
3.  
V
reference levels throughout this data sheet refer to VCC if that is where the power supply connection is made, or V  
if VCC is connected to ground.  
CC  
CAP  
4. CE > V does not produce standby current levels until any nonvolatile cycle in progress has timed out.  
IH  
Document Number: 001-51000 Rev. **  
Page 6 of 14  
 
   
STK22C48  
Capacitance  
In the following table, the capacitance parameters are listed.  
Parameter  
Description  
Input Capacitance  
Output Capacitance  
Test Conditions  
Max  
8
Unit  
pF  
C
C
T = 25°C, f = 1 MHz,  
CC  
IN  
A
V
= 0 to 3.0V  
7
pF  
OUT  
Thermal Resistance  
In the following table, the thermal resistance parameters are listed.  
28-SOIC  
(300 mil)  
28-SOIC  
(330 mil)  
Parameter  
Description  
Test Conditions  
Unit  
ΘJA  
Thermal Resistance  
(Junction to Ambient)  
Test conditions follow standard test methods  
and procedures for measuring thermal  
impedance, per EIA / JESD51.  
TBD  
TBD  
°C/W  
ΘJC  
Thermal Resistance  
(Junction to Case)  
TBD  
TBD  
°C/W  
Figure 6. AC Test Loads  
R1 963Ω  
R1 963Ω  
For Tri-state Specs  
5.0V  
5.0V  
Output  
Output  
R2  
R2  
512  
30 pF  
5 pF  
512Ω  
Ω
AC Test Conditions  
Input Pulse Levels....................................................0V to 3V  
Input Rise and Fall Times (10% to 90%)...................... <5 ns  
Input and Output Timing Reference Levels.................... 1.5V  
Note  
5. These parameters are guaranteed by design and are not tested.  
Document Number: 001-51000 Rev. **  
Page 7 of 14  
 
 
STK22C48  
AC Switching Characteristics  
SRAM Read Cycle  
Parameter  
25 ns  
45 ns  
Description  
Unit  
Cypress  
Alt  
Min  
Max  
Min  
Max  
Parameter  
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
Chip Enable Access Time  
Read Cycle Time  
25  
45  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ACE  
ELQV  
t
25  
45  
RC  
AA  
AVAV, ELEH  
[7]  
Address Access Time  
25  
10  
45  
20  
AVQV  
Output Enable to Data Valid  
Output Hold After Address Change  
Chip Enable to Output Active  
Chip Disable to Output Inactive  
Output Enable to Output Active  
Output Disable to Output Inactive  
Chip Enable to Power Active  
Chip Disable to Power Standby  
DOE  
OHA  
GLQV  
5
5
5
5
AXQX  
[8]  
[8]  
LZCE  
HZCE  
LZOE  
HZOE  
ELQX  
10  
10  
25  
15  
15  
45  
EHQZ  
0
0
0
0
GLQX  
GHQZ  
PU  
ELICCH  
EHICCL  
PD  
Switching Waveforms  
[6, 7]  
Figure 7. SRAM Read Cycle 1: Address Controlled  
W5&  
$''5(66  
W$$  
W2+$  
'4ꢀꢊ'$7$ꢀ287ꢋ  
'$7$ꢀ9$/,'  
[6]  
Figure 8. SRAM Read Cycle 2: CE and OE Controlled  
W5&  
$''5(66  
&(  
W$&(  
W3'  
W+=&(  
W/=&(  
2(  
W+=2(  
W'2(  
W/=2(  
'4ꢀꢊ'$7$ꢀ287ꢋ  
'$7$ꢀ9$/,'  
$&7,9(  
W38  
67$1'%<  
,&&  
Notes  
6. WE and HSB must be High during SRAM Read cycles.  
7. Device is continuously selected with CE and OE both Low.  
8. Measured ±200 mV from steady state output voltage.  
Document Number: 001-51000 Rev. **  
Page 8 of 14  
 
     
STK22C48  
SRAM Write Cycle  
Parameter  
25 ns  
45 ns  
Description  
Write Cycle Time  
Unit  
Cypress  
Alt  
Min  
Max  
Min  
Max  
Parameter  
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
25  
20  
20  
10  
0
45  
30  
30  
15  
0
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
WC  
AVAV  
t
Write Pulse Width  
PWE  
SCE  
SD  
WLWH, WLEH  
t
Chip Enable To End of Write  
Data Setup to End of Write  
Data Hold After End of Write  
Address Setup to End of Write  
Address Setup to Start of Write  
Address Hold After End of Write  
Write Enable to Output Disable  
Output Active After End of Write  
ELWH, ELEH  
t
DVWH, DVEH  
t
HD  
WHDX, EHDX  
t
20  
0
30  
0
AW  
AVWH, AVEH  
t
SA  
AVWL, AVEL  
t
0
0
HA  
WHAX, EHAX  
[8,9]  
10  
14  
HZWE  
LZWE  
WLQZ  
WHQX  
5
5
Switching Waveforms  
Figure 9. SRAM Write Cycle 1: WE Controlled  
tWC  
ADDRESS  
CE  
tHA  
tSCE  
tAW  
tSA  
tPWE  
WE  
tHD  
tSD  
DATA VALID  
DATA IN  
tHZWE  
tLZWE  
HIGH IMPEDANCE  
PREVIOUS DATA  
DATA OUT  
Figure 10. SRAM Write Cycle 2: CE Controlled  
tWC  
ADDRESS  
tHA  
tSCE  
tSA  
CE  
WE  
tAW  
tPWE  
tSD  
tHD  
DATA IN  
DATA VALID  
HIGH IMPEDANCE  
DATA OUT  
Notes  
9. If WE is Low when CE goes Low, the outputs remain in the high impedance state.  
10. HSB must be high during SRAM Write cycles.  
11.  
CE or WE must be greater than V during address transitions.  
IH  
Document Number: 001-51000 Rev. **  
Page 9 of 14  
 
     
STK22C48  
AutoStore or Power Up RECALL  
STK22C48  
Max  
Parameter  
Alt  
Description  
Unit  
Min  
t
t
t
t
t
t
Power up RECALL Duration  
STORE Cycle Duration  
550  
10  
μs  
ms  
μs  
V
HRECALL  
RESTORE  
HLHZ  
STORE  
DELAY  
t
Time Allowed to Complete SRAM Cycle  
Low Voltage Trigger Level  
Low Voltage Reset Level  
1
HLQZ , BLQZ  
V
V
4.0  
4.5  
3.6  
300  
SWITCH  
V
RESET  
t
Low Voltage Trigger (V  
) to HSB Low  
ns  
VSBL  
SWITCH  
Switching Waveform  
Figure 11. AutoStore/Power Up RECALL  
WE  
Notes  
12. t  
starts from the time V rises above V  
.
SWITCH  
HRECALL  
CC  
13. CE and OE low for output behavior.  
14. CE and OE low and WE high for output behavior.  
15. HSB is asserted low for 1us when V  
takes place.  
drops through V  
. If an SRAM Write has not taken place since the last nonvolatile cycle, HSB is released and no store  
CAP  
SWITCH  
Document Number: 001-51000 Rev. **  
Page 10 of 14  
 
       
STK22C48  
Hardware STORE Cycle  
STK22C48  
Min Max  
Parameter  
Alt  
Description  
Unit  
t
t
t
t
t
t
Hardware STORE High to Inhibit Off  
Hardware STORE Pulse Width  
700  
ns  
ns  
ns  
DHSB  
RECOVER, HHQX  
15  
PHSB  
HLBL  
HLHX  
Hardware STORE Low to STORE Busy  
300  
Switching Waveform  
Figure 12. Hardware STORE Cycle  
Note  
16. t  
is only applicable after t  
is complete.  
STORE  
DHSB  
Document Number: 001-51000 Rev. **  
Page 11 of 14  
 
 
STK22C48  
STK22C48 - N F 45 I TR  
Packaging Option:  
TR = Tape and Reel  
Blank = Tube  
Temperature Range:  
Blank - Commercial (0 to 70°C)  
I - Industrial (-40 to 85°C)  
Speed:  
25 - 25 ns  
45 - 45 ns  
Lead Finish  
F = 100% Sn (Matte Tin)  
Package:  
N = Plastic 28-pin 300 mil SOIC  
S = Plastic 28-pin 330 mil SOIC  
Ordering Information  
Speed (ns)  
Ordering Code  
STK22C48-NF25TR  
STK22C48-NF25  
Package Diagram  
51-85026  
51-85026  
51-85058  
51-85058  
51-85026  
51-85026  
51-85058  
51-85058  
51-85026  
51-85026  
51-85058  
51-85058  
51-85026  
51-85026  
51-85058  
51-85058  
Package Type  
28-pin SOIC (300 mil)  
28-pin SOIC (300 mil)  
28-pin SOIC (330 mil)  
28-pin SOIC (330 mil)  
28-pin SOIC (300 mil)  
28-pin SOIC (300 mil)  
28-pin SOIC (330 mil)  
28-pin SOIC (330 mil)  
28-pin SOIC (300 mil)  
28-pin SOIC (300 mil)  
28-pin SOIC (330 mil)  
28-pin SOIC (330 mil)  
28-pin SOIC (300 mil)  
28-pin SOIC (300 mil)  
28-pin SOIC (330 mil)  
28-pin SOIC (330 mil)  
Operating Range  
25  
Commercial  
STK22C48-SF25TR  
STK22C48-SF25  
STK22C48-NF25ITR  
STK22C48-NF25I  
STK22C48-SF25ITR  
STK22C48-SF25I  
STK22C48-NF45TR  
STK22C48-NF45  
Industrial  
45  
Commercial  
Industrial  
STK22C48-SF45TR  
STK22C48-SF45  
STK22C48-NF45ITR  
STK22C48-NF45I  
STK22C48-SF45ITR  
STK22C48-SF45I  
All parts are Pb-free. The above table contains Final information. Please contact your local Cypress sales representative for availability of these parts  
Document Number: 001-51000 Rev. **  
Page 12 of 14  
 
STK22C48  
Package Diagrams  
Figure 13. 28-Pin (300 mil) SOIC (51-85026)  
NOTE :  
PIN 1 ID  
1. JEDEC STD REF MO-119  
2. BODY LENGTH DIMENSION DOES NOT INCLUDE MOLD PROTRUSION/END FLASH,BUT  
DOES INCLUDE MOLD MISMATCH AND ARE MEASURED AT THE MOLD PARTING LINE.  
MOLD PROTRUSION/END FLASH SHALL NOT EXCEED 0.010 in (0.254 mm) PER SIDE  
14  
1
MIN.  
3. DIMENSIONS IN INCHES  
MAX.  
0.291[7.39]  
0.300[7.62]  
4. PACKAGE WEIGHT 0.85gms  
*
0.394[10.01]  
0.419[10.64]  
PART #  
15  
28  
0.026[0.66]  
0.032[0.81]  
S28.3 STANDARD PKG.  
SZ28.3 LEAD FREE PKG.  
SEATING PLANE  
0.697[17.70]  
0.713[18.11]  
0.092[2.33]  
0.105[2.67]  
*
0.004[0.10]  
0.0091[0.23]  
0.015[0.38]  
0.050[1.27]  
0.013[0.33]  
0.019[0.48]  
*
0.004[0.10]  
0.0125[3.17]  
0.050[1.27]  
TYP.  
0.0118[0.30]  
51-85026-*D  
Figure 14. 28-Pin (330 mil) SOIC (51-85058)  
51-85058-*A  
Document Number: 001-51000 Rev. **  
Page 13 of 14  
 
STK22C48  
Document History Page  
Document Title: STK22C48 16 Kbit (2K x 8) AutoStore nvSRAM  
Document Number: 001-51000  
Orig. of  
Change  
Submission  
Date  
Rev.  
ECN No.  
Description of Change  
**  
2625139  
GVCH/PYRS  
01/30/09  
New data sheet  
Sales, Solutions, and Legal Information  
Worldwide Sales and Design Support  
Cypress maintains a worldwide network of offices, solution centers, manufacturer’s representatives, and distributors. To find the office  
closest to you, visit us at cypress.com/sales.  
Products  
PSoC  
PSoC Solutions  
General  
Clocks & Buffers  
Wireless  
Low Power/Low Voltage  
Precision Analog  
LCD Drive  
Memories  
Image Sensors  
CAN 2.0b  
USB  
© Cypress Semiconductor Corporation, 2006-2009. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of  
any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be used for  
medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its products for use as  
critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress products in life-support systems  
application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges.  
Any Source Code (software and/or firmware) is owned by Cypress Semiconductor Corporation (Cypress) and is protected by and subject to worldwide patent protection (United States and foreign),  
United States copyright laws and international treaty provisions. Cypress hereby grants to licensee a personal, non-exclusive, non-transferable license to copy, use, modify, create derivative works of,  
and compile the Cypress Source Code and derivative works for the sole purpose of creating custom software and or firmware in support of licensee product to be used only in conjunction with a Cypress  
integrated circuit as specified in the applicable agreement. Any reproduction, modification, translation, compilation, or representation of this Source Code except as specified above is prohibited without  
the express written permission of Cypress.  
Disclaimer: CYPRESS MAKES NO WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, WITH REGARD TO THIS MATERIAL, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES  
OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. Cypress reserves the right to make changes without further notice to the materials described herein. Cypress does not  
assume any liability arising out of the application or use of any product or circuit described herein. Cypress does not authorize its products for use as critical components in life-support systems where  
a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress’ product in a life-support systems application implies that the manufacturer  
assumes all risk of such use and in doing so indemnifies Cypress against all charges.  
Use may be limited by and subject to the applicable Cypress software license agreement.  
Document Number: 001-51000 Rev. **  
Revised January 30, 2009  
Page 14 of 14  
AutoStore and QuantumTrap are registered trademarks of Cypress Semiconductor Corporation. All products and company names mentioned in this document may be the trademarks of their respective  
holders.  
 

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